1. Field of the Disclosure
The present invention relates to electronic devices and processes for forming electronic devices, and more particularly, to electronic devices including transistor structures with sidewall spacers and processes for forming the electronic devices.
2. Description of the Related Art
Semiconductor-on-insulator (“SOI”) architectures are becoming the more common as electronic and device performance requirements continue to be more demanding. P-channel and n-channel transistors formed using an SOI substrate typically include active regions that have channel lengths and channel widths along <110> crystal directions. Carrier mobility within the channel regions of the p-channel and n-channel transistors is an area for continued improvement.
Many approaches use different widths of sidewall spacers to affect the performance of the transistors. For example, relatively narrower sidewall spacers can be formed adjacent to gate electrodes of n-channel transistors, and relatively wider sidewall spacers can be formed adjacent to gate electrodes of p-channel transistors. The different widths of sidewall spacers can involve additional or more complex processing operations and result in transistors, particularly p-channel transistors that may need to be designed wider to account for the wider sidewall spacers. Lower component density and decreased yield may occur with the sidewall spacers of differing widths.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.